3-dimensional (3D) packaging technology Essay

Introduction 3-dimensional (3D) packaging technology is a method used to provide volumetric packaging solution in products. This technology uses the height, otherwise known as the third or z-dimension, for achieving higher levels of integration and performance in the products. 3D technology chiefly helps in the space-efficient integration of the multi-media functions in the products. The present trend among the consumers is to look out for products, having the maximum functionality in the smallest and lightest possible package. This demand for more functions in the smallest volume, calls for higher memory capacity, which in turn demands more complex and efficient architectures. In addition, the new product designs in digital handbook, cell phones, digital cameras, PDAs and music players, require that these features are integrated using innovative technical form factors and architectures. See more: Social process essay The 3D packaging in recent times has been associated with the delivering of the highest level of silicon integration and area efficiency at the lowest cost, smallest size and best performance.   This has resulted in higher growth and brought in newer applications, for the technology. This growth trend in the 3D technology can be seen since the year 1995. Prior to this, the most efficient and economic way to provide more functionality to an electronic system was to integrate all these functions onto the individual chips using the system on Chip, SOC. However, this method was becoming costlier and also less efficient, as the number of functions to be integrated in a single chip further increased. In addition, some chips that could be integrated together logically were mechanically incompatible, due to the different die materials used. The present day technologies in high density packaging have reached a very advanced stage. Now a single chip system can be very efficiently split into multiple dies, so as to provide better performance at lower manufacturing costs. Over the past few years, die stacking has emerged as a powerful packaging option for satisfying challenging IC packaging requirements. It works by integrating chips vertically in a single package. This increases the amount of silicon per unit area, which leads to a smaller package footprint, hence conserving system-board real estate. In addition, it enables shorter routing interconnects from chip to chip, speeding the signaling between them. Heterogeneous devices can also be stacked using this technology. There is an additional benefit of the simplification of surface-mount system-board assembly, due to the lesser number of components being placed on the board. Vias – Due to the increasing number of dies in a stack, the designers are facing the challenge of meeting the temperature design specification. One method to counter this is to provide a thermal path from each individual die to a substrate using thermal vias. These thermal vias can be implemented using several methods. One of the approaches is to have a thermal die that thermally connects each die to the substrate. The heat from each die is conducted rapidly from one end of the board to another, either through the die attach or the vias. Thermal vias are made of copper runs providing the a path of least thermal resistance, and so heat is transferred through the vias in a proportion much greater than the area of the vias. Usually one end of via is attached to the IC and the other end is attached to a heat sink. Thermal vias work very well with flip-chip devices. With no additional space required for the heat conduction, these are considered as a mini-thermal solution. Through Silicon Vias – Through silicon vias, TSVs, are vertical structures in between the chips that are used as an interconnection to eliminate the existing wire bonds. These allow for the shortest electrical path between two sides of wafers or die, used for 3D die-to-die, die-to-wafer, MEMS wafer level packaging. A TSV, 3-D chip stacking process hence provides a means of implementing complex, multi chip systems entirely in silicon. TSVs. By the vertical stacking of the blocks using this technology, the wire length of interconnects can significantly be reduced. Vias provide both electrical and thermal path. In this paper, the thermal enhancement realized by the vias is discussed along with trying to find out a way to remove heat from the dies. The power applied to the dies is between 5-10 watts power. We found that one such method was to use silicon dies.    Objective of the Study The methodology of the present study will be explained in detail in the next section. The study focuses on the following points: A study was made on the heat transfer enhancement of the stacked die geometry using Through Silicon vias, TSVs, on the die pad location. Different schemes were studied. The use of the TSVs to reduce the maximum junction temperature accumulated at the wafers was studied The exact placement of vias   to optimize thermal management, was done Finally, a study of the thermo-mechanical issues, which occurred when TSVs are used, was made. Methodology The figure below explains the methodology used for this study. First, the package components including the vias were created using Pro /Engineer Wildfire. After this the material property was defined and the various components were assembled. The entire geometry and the properties were then imported to Ansys workbench. Here, the Boundary conditions were defined and implemented. Finally, the end result, which is the thermal enhancement of the die geometry, was evaluated. Modeling Methodology Any device’s thermal properties can be expressed as a part of an electrical circuit diagram. If, ÃŽ ¸JA is the thermal resistance between junction, and ambience given in â„Æ'/W, then mathematically ÃŽ ¸JA can be expressed as bewlow: The geometry is created using Pro-e, as mentioned in the previous section. Here, every element should be saved in the UDF library. This is done, so as to make it possible to retrace various parts for assembly. In this assembly area, the area contact is done using the mate option, and the vertical and horizontal lines can be joined using the align option. For the analysis, a molded Ball Grid Array, BGA, stacked package has been considered. The package substrate is 9Ãâ€"9 mm in area and is 0.3 mm thick. A fully populated solder ball matrix with a ball count of 56 and a pitch of 0.8 mm is used. The stand off height after reflow is 0.2 mm. The thickness of the mold compound cap is 1.20 mm with the same dimensions as the package substrate. The diameter of the thermal vias is 0.20mm and its thickness is 0.86mm. The stacked packages have 16 vias and 9 vias. This paper compares the junction temperature of stacked dice with and without vias. Three different package architectures were modeled, viz. [a] Stacked with spacers die, [b] Rotated stack die, [b] Pyramid stack die as shown in figure. Three non-volatile dies measuring 6.4Ãâ€"4.8 mm, with a thickness of 0.2 mm, form the spacer die. Die thickness is 0.25mm in rotated die. The bottom PCB is made of a die measuring 32Ãâ€"24 mm, with a thickness of 0.6 mm. In the spacer stack die, dummy die is 5.6Ãâ€"4.0, with a thickness of 0.08mm. For this paper, solderball geometry is modeled closely approximating the real solderball. In solderball geometry, mid diameter is 0.43mm, and top and bottom diameter is 0.33mm, with a height of 0.33mm. Solderball distance is 0.8mm. These dimensions are not specific to a particular package. They are based on values found in present market for a typical molded BGA stack package. The details of the package dimensions and material properties of the components is shown in the below. Simulation and Case Studies While doing the Simulation using the Ansys workbench, the following boundary conditions need to be applied to all the faces of the modeling and to the PCB. The film coefficient is 10W/m ²  ºC and the Ambient Temperature is 50 ºC. Also a power of 0.3 W ia applied to each of the three dies. By dividing area 0.3W / 6.5Ãâ€"4.8 (Die area), we can get a heat flux as 9765 W/m ². The main physics behind the technology is providing a smooth and effective heat transfer path. Due to the high thermal conductivity of the copper i.e. the thermal vias, a proportion of the heat much greater than the surface area of the vias will be transferred. As mentioned in the section above, for the baseline simulation, an effective heat transfer coefficient of 10 W/m ²- ºC with 50 ºc ambient temperature was applied on the top of the mold cap, and the top and bottom surfaces of the circuit board. For all the three types of stacks, the result was a junction temperature of 116.2 ºC with no vias. When 9 vias were included, for the same heat transfer coefficient, the junction temperature was reduced to 111.7 ºC, results in a decrease of around 3.6% of the maximum temperature in each of the architectures. By increasing via count to 16 we got the junction temperature to 110.7 ºC effectively reducing the junction temperature by 4.49% of the maximum temperature in each of packaging. The figure below explains the proportional vector plot of heat flux in ANSYS Workbench, where the heat flow path can be seen, which densely collects at the via location. This heat flux is a negative heat flux which is flowing away from the surface and takes away energy out of the body in the form of heat Vias can also provide a means of customizing the heat transfer process for devices with a highly non-uniform power distribution. This is especially important for high density interconnects where the device has highly non-uniform power map. Test Cases There were 12 case studies conducted on the simulation test tool. As mentioned earlier, each case was tested with and without vias, and the corresponding temperature plot was drawn. In each case the maximum and minimum temperatures achieved were also noted. For one of the cases it was found that the particular test case no 11 gave a lesser temperature, in the range of 60-70 degrees. The following is a description of the 12 test cases: Case 1 – The first case consisted of the Dies showing the temperature plot at the film coefficient of 200W/m ²Ã‚ ºC. The power applied to the top die, die with vias and the bottom die was 6watts, 2watts, and 2 watts respectively. The maximum temperature achieved was 316.459  ºC and the minimum temperature was 269.908  ºC. Applying same conditions without vias gave the maximum temperature as 317.2  ºC and minimum temperature as 269.591  ºC. Case 2 – For the second case, the Boundary conditions applied were a film co-efficient of 200W/m ²Ã‚ ºc and Power of 2 watts applied equally on all the three dice. The maximum temperature achieved was 216.363  ºC and the minimum temperature was 169.568  ºC. Applying same conditions without vias gave the maximum temperature as 217.140  ºC and minimum temperature as 169.55  ºC. Case 3 – For this case, copper was used as the substrate mask and the film coefficient was 400 W/m ²c º. The maximum temperature achieved was 178.739  ºC and the minimum temperature was 144.488  ºC. Applying same conditions without vias gave the maximum temperature as 179.426  ºC and minimum temperature as 144.463  ºC. The Observation of the above results showed that the temperature difference with and without Vias was only 1 ºC. Case 4 – For this case, convection was applied on board and top die. The power applied to on top, middle and bottom dies was 4watts, 3watts, and 3watts respectively. The maximum temperature achieved was 93.775  ºC and the minimum temperature was 36.098  ºC. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 93.911  ºC and minimum temperature as 36.105  ºC. Case 5 – For this case, the Film co-efficient of 400W/m ²c º on top of the top die and 15W/m ²c º on the Pwb. Also 5watts power was applied to each of the dies. The maximum temperature achieved was 209.345  ºC and the minimum temperature was 128.857  ºC. It was seen that the minimum Temperature occurs at the top die where the vias were present. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 210.878  ºC and minimum temperature as 128.739  ºC, i.e. a drop of only 1.6  ºC was observed. Case 6 – For this case, germanium die was used, instead of silicon die. The maximum temperature achieved was 223.052  ºC and the minimum temperature was 118.468  ºC. Applying same conditions without vias gave very slight change in the plot, the maximum temperature as 225.219  ºC and minimum temperature as 118.286  ºC, i.e. a drop of 2.6  ºC in the Junction temperature was observed. Case 7 – For this case, the Film co-efficient on board was 300 W/m ²c º, the Film co-efficient on top surface was 400W/m ²Ã‚ ºc, and 5 watts power applied on both dies. The maximum temperature achieved was 119.575  ºC and the minimum temperature was 43.411  ºC. Applying same conditions without vias gave the maximum temperature as 120.076  ºC and minimum temperature as 43/504  ºC. The maximum change in Junction temperature, with and without vias was observed.0.5  ºC. Case 8 – In this case, a very high thermal conductive material has been used For the through silicon vias (ie.600 W/m ºc). The maximum temperature achieved was 119.575  ºC and the minimum temperature was 43.411  ºC. Applying same conditions without vias gave the maximum temperature as 95.315  ºC and minimum temperature as 36.347  ºC. The maximum temperature between i.e. a drop of 2.6  ºC in the Junction temperature was observed.0.5  ºC. Though high conductive vias were used there is no significant drop in the maximum temperature in the dice. Case 9 – The following case used TSVs with the application of higher power( 7 watts) on the top die than the Other two dice i.e.., 2 watts on the die with vias and 1 watt on the bottom Die. The maximum temperature achieved was 97.657  ºC and the minimum temperature was 39.063  ºC. Applying same conditions without vias gave the maximum temperature as 97.889  ºC and minimum temperature as 39.032  ºC. As seen, the TSVs made a vnegligile difference of 0.5  ºC. Case 10 – In this case, the total power on the dice was 5 watts and the power on the die with vias was 5 watts. The maximum temperature achieved was 61.754  ºC, which was the least temperature, and the minimum temperature was 29.576  ºC. Applying same conditions without vias gave the maximum temperature as 61.871  ºC and minimum temperature as 29.55  ºC. Case 11– In this case, the substrate and substrate mask thickness is drastically reduced to 0.075mm and 0.085mm. The maximum temperature achieved was 93.697  ºC and the minimum temperature was 36.079  ºC. Applying same conditions without vias gave the maximum temperature as 93.775  ºC and minimum temperature as 36.067  ºC. Case 12 – In this case, the simulation was done by applying high power of 6 watts on the top die and 2 watts each on the middle and bottom die. The maximum temperature achieved was 88.320  ºC and the minimum temperature was 35.481  ºC. Applying same conditions without vias gave the maximum temperature as 88.512  ºC and minimum temperature as 35.445  ºC. Conclusion In this paper elaborate study has been done in analyzing the effect of thermal vias on the die and ways to bring down the junction temperature by reduce count. Thermal enhancement was tested by running the thermal simulation with various test cases, and also with / without thermal vias. The Temperature profile of the entire stacked die geometry was plotted in Ansys Workbench. It was found that Thermally Through Silicon vias in this particular package did not give a significant effect on performance because of less area of vias and package construction. The use of silicon die did give a lesser temperature as compared to other materials. Future studies will focus on doing the stress analysis of this package with vias, using techniques like thermal shocks for profiling the thermal properties this package in further detail.